The output buffer circuits of an integrated circuit device are characterized by relatively large current drive and power capacity for applying the results of internal logic circuitry to an external load. Such buffer circuits 10,11 may be indicated by the schematic representations of FIGS. 1 and 2 showing respectively non-inverting 10 and inverting 11 output buffer circuits. The non-inverting tristate output buffer circuit 10 delivers output signals with high H and low L potential states at the output V.sub.OUT in response to respective input signals of high H and low L potential states at the input V.sub.IN. Conversely, the inverting tristate output buffer circuit 11 delivers inverted output signals of low L and high H potential states at the output V.sub.OUT. The output buffer circuits have characteristic propagation delay times tpHL, tpLH for respective transitions from high to low HL and low to high LH potential states at the output V.sub.OUT.
The tristate output buffer circuits 10,11 include tristate enable circuitry with a tristate enable input 14. The tristate enable circuit causes a high impedance third state Z at the output V.sub.OUT of the output buffer circuits 10,11 in response to a high potential level tristate enable signal OEB at the tristate enable input 14. Applying the high impedance third state Z at the output V.sub.OUT is referred to herein as "tristating" the output buffer circuit. The tristate condition is useful when the tristate output buffer circuit is coupled to a common bus. The tristate condition provides a "quiet" output when other output buffer circuits are active on the common bus. Bipolar TTL tristate output buffer circuits with tristate enable circuits are illustrated in U.S. Pat. Nos. 5,051,623; 4,649,297; 4,677,320; 4,661,727; & 4,581,550. CMOS tristate output buffer circuits with CMOS tristate enable circuits are shown in U.S. Pat. Nos. 5,036,222; 5,049,763 (FIG. 24); 4,961,010; and U.S. patent application Ser. No. 483,927 filed Feb. 22, 1990.
The output buffer circuits 10,11 are coupled between high and low potential power rails V.sub.CC, GND for controlled sourcing and sinking of current at the output V.sub.OUT. In the case of a prolonged short circuit condition of the output shorted to the high or low potential power rail, uncontrolled current flow may lead to extended electrical overload, heating, and damage to integrated circuit devices coupled to the output.
Short circuit current protection from large transient currents has been provided by coupling a resistor in series with the output to limit the amount of current in the event of a transient short circuit condition at the output. Alternatively active techniques have been used to shunt current away from the base of an output transistor to limit output current in the event of a large transient short circuit current.
For extended electrical overload resulting from a prolonged short circuit condition at the output, thermal sensing has been used. A large temperature gradient across an integrated circuit die or a high temperature is detected and the circuit is shut down before thermal damage occurs. A disadvantage of the thermal shutdown short circuit protection is the slow response time in the order of milliseconds.